# MOS current mirrors

A bit of the theory about MOS current mirror types:

A very basic current mirror is shown in picture about, for a transistor in the saturation mode we have:

We know that for this mode: Vds >= Vin – Vth, then the left transistor is automaticaly in the saturation, Vin is the same for both transistors (if they are in saturation):
$\dfrac {I_{D0}} {I_{D1}}=\dfrac {\dfrac {W_{0}} {L_{0}}} {\dfrac {W_{1}} {L_{1}}}$

The channel length modulation effect has not been taken into account, this is not important for a moment, let me build the output current plot:

We can approximate the saturation mode Vds entry at about 400mV, the whole curve doesn’t look quite good – if we want to move the current source closer to the ideal one, then we expect to have straight curve after the saturation, the slope indicates that we don’t have large output resistance. Lets rewrite Vds min as:

That’s mean that we can decrease the saturation entry threshold by either increasing of transistor sizes, either by decreasing the drain current. For instance, I have increased widths of both transistors 10x:

The threshold moved lower, but the output resistance becomes worse, plus the channel length modulation takes place as well (the output current is depended on Vds).

Now, let me add resistors to source of transistors:

By the Kirchhoff’s circuit law:

Vgs0 – I0R0 = Vgs1 – I1R1, and if transistors are the same then I0R0 = I1R1 -> the current depends only on the resistors ratio. But the main feature of the circuit is a boosting of the output resistance by approx. gm*R times, lets take a look at the output current for this circuit:

The biggest disadvantage of this circuit is increasing of Vdsmin to (Vgs-Vth)+IR, for our particular case the vdsmin is larger at 100u*1K = 100mV, which is visible on the plot. The plot also clearly shows that slope has been decreased. But still not quite enoug.

The situation is much better for a cascode current source:

As always, the mirroring ration is determined by the closest to the ground element. Let me plot the output current for this guy:

Assume that all transistors have the same size, then we can say that the threshold voltage is equal for all of them and it is Vth. Now let me write the minimum drain to source voltage for the M4 transistor:

Or, it can be rewritten as:

i.e.

$V_{outmin}=V_{x}-V_{th}$ , and Vx

$V_{outmin}=V_{gs3}+V_{gs1}-V_{th}$  then we could write the minimum output voltage:

Thus, in order to reduce the output min voltage we need either to decrease the current, either increase the transistor sizes. Since the size is under square root sign it will take a good amount of the area to achieve the desired result. For instance, I have increased sizes 20x:

The voltage has decreased for sure, but it is still equal to ~750mV, which is a lot. Though an output resistance looks perfect…

Now take a look at the another circuit:

Let me call some voltages – Vod1 = Vod2 = Vod = Vgs-Vth.

Now take a look at the N5 transistor, if the sourcing current also equal to I, then:

Analogical for N0 and N3 – Vod0 = Vod3 = n*Vod, now calculate Vds1:

Vds1 = Vg5 – nVod = (n+1)Vod-nVod = Vod

then Vds0 = Vg5 – Vod = nVod.

If n = 1, then Vdsmin = 2Vod:

We have got a wonderful current source. I should mention though, this current source and equations should be considered with a long channel devices. For a short channel, or for fin fets, the pictures will be quite ugly from the current source perspective. But they are good for different things