In maestro view, Simulation Files, then add to definition file your_file.txt
The file content:
simulator lang = spectre save so_* exclude=[*:*_so_* *other net"]
Saving nets with file in cadence virtuoso
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Category Archives: IC design
Verilog-A: A comparator
Creating of a comparator model is described below.
What we need from a comparator usually?
- The high level value
- Slew Rate
- Hysteresis
Verilog-A: A PWM controller
Below is the procedure of a PWM veriloga controller created in Verilog-A language (behavioral description language)
So, I need a PWM controller which is basically the block the duty cycle of which will vary in dependence of the control pin voltage. The previous picture shows the output of the controller (red) with input applied control voltage (green). The frequency is constant.
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